FEATURES • Only 47 single word instructions • All instructions are single cycle except for program branches which are two-cycle • 13-bit wide instructions • 8-bit wide data path • 5-level deep hardware stack • 4K x 13 bits on chip EPROM/ROM • 140 x 8 bits on chip general purpose registers (SRAM) • Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle • Direct, indirect addressing modes for data accessing • One 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler • Three 8-bit real time clock/counter (Timer1, Timer2, and Timer3) with period setting • Internal Power-on Reset (POR) • Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR) • Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST) • On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control • Five I/O ports (38 I/O pins) with independent direction control • 32 programmable p